1. Field of the Invention
The present invention relates to a semiconductor integrated circuit operable to suppress a leak current in a MOS transistor with a reduced influence on operating time of the circuit.
2. Description of the Related Art
A MOS transistor having a gate length of 62 nm or less brings about an increase in short channel effect-caused leak current in the MOS transistor. A semiconductor circuit device consumes electrical power equal in value to a total of a dynamic component such as switching and charge/discharge associated with the operation of the circuit, and a statistic component such as the leak current.
The 65 nm or more semiconductor process art is operable to reduce the power source voltage of the circuit in response to a reduction in threshold voltage of the MOS transistor, thereby reducing dynamic consumption current, with a consequential reduction in power consumption. However, for the 65 nm or less semiconductor process art, the leak current in the MOS transistor accounts for a large percentage of the total consumption current.
A leak current-suppressing method includes a step of reducing the power source voltage or applying bias voltage to either a source or substrate of the MOS transistor. However, the reduced power source voltage results in reduced driving capability of the MOS transistor, and the circuit is thereby operated at lower speed.
An improved semiconductor integrated circuit designed to consume less electrical power is proposed by cited Reference No. 1 or published Japanese Patent Laid-Open No. 2004-96073 (FIGS. 1 and 4).
Referring to FIG. 11, a prior art semiconductor integrated circuit is illustrated in block diagram form. Referring to FIG. 12, a course of action provided by the prior art semiconductor integrated circuit is illustrated in flowchart form. FIGS. 11 and 12 are disclosed in cited Reference No. 1.
The semiconductor integrated circuit includes a processor 100, an operating mode control unit 101, and a bias-switching circuit 102. The processor 100 is of a dual mode type: a waiting mode in which the leak current is suppressed; and a regular mode in which the circuit is usually operated. The operating mode control unit 101 has control of a switchover of the processor 100 between the waiting and regular modes. The operating mode control unit 101 includes a timer 103.
When switching over the processor 100 from the regular mode to the waiting mode, the operating mode control unit 101 notifies the bias-switching circuit 102 of the switchover. The bias-switching circuit 102 changes a value of the bias voltage when the processor 100 is in the waiting mode. The bias voltage is to be applied to the MOS transistor at either a source or substrate terminal thereof. While the bias voltage is applied to the MOS transistor, a difference in potential between the source of the MOS transistor and a gate thereof is reduced to reduce the leak current, thereby providing reduced power consumption.
When the bias voltage is changed in value, then there is a need to charge and discharge parasitic capacity that accompanies the MOS transistor at the source or substrate thereof. The circuit is rendered inoperative during the charge and discharge of the parasitic capacity, and the processor 100 is deactivated during that time. The timer 103 measures a period of time in which the parasitic capacity is charged and discharged, thereby practicing time management. When the period of time as managed by the timer 103 is terminated, then the processor 100 starts a course of action. In other words, the processor 100 still remains inoperative during a period of time in which the parasitic capacity must be charged and discharged, even when the processor 100 is switched over from the waiting mode to the regular mode.
As shown by the flowchart of FIG. 12, the switchover from the waiting mode to the regular mode is completed after timer-out or the elapse of the time period measured by the timer 103. The semiconductor integrated circuit as disclosed by cited Reference No. 1 makes it feasible to balance low power consumption with operating speed.
However, according to the prior art, the parasitic capacity accompanying the MOS transistor must be charged and discharged when the processor 100 is switched over from the waiting mode to the regular mode. As a result, the circuit, including the processor 100, cannot be operated during such a period of time as to require the charge/discharge of the parasitic capacity, after the switchover from the waiting mode to the regular mode. In short, the circuit cannot be operated for a certain period of time after the processor 100 is changed over to the regular mode.
Such temporary downtime of the processor 100 results in reduced operating speed of the entire system including the semiconductor integrated circuit.
A larger-scaled circuit experiences a greater load, resulting in the charge/discharge in a longer period of time. More specifically, a problem with the prior art circuit is that a larger-scaled circuit involves charge/discharge-caused, longer downtime when the circuit is switched over from the waiting mode to the regular mode. The problem makes it difficult to set up the waiting mode for a short period of downtime that takes places during a continuous course of action such as audio or image processing.